Automated or automatic test systems are widely used by manufacturers in the electronics industry to test various devices, including electronic components and ICs, to cull defective devices before they are incorporated in products. Broadly, there are three types of digital devices that are commonly tested using automated test systems, those having memory arrays or circuits, such as flash memory or random access memories (RAM), those having logic circuits, such as micro controllers, application specific ICs (ASICs) and programmable logic devices (PLDs), and those having both memory circuits and logic circuits. Generally, it is desirable to test the devices at several points during the manufacturing process including while they are still part of a wafer or substrate, and after packaging the devices but before they are mounted or assembled on modules, cards or boards. This repetitive testing imposes demands on automated test systems to perform tests at high speed and with a high degree of accuracy. Moreover, the trend in the electronics industry has been to further increase the miniaturization of electronic devices and circuits, thereby allowing for an increase in the complexity of the devices. As the devices become more complex, the complexity of the test systems and their cost increase correspondingly.
Test systems have traditionally been packaged in fixed sized chassises with a defined maximum pin count for each chassis size. To expand to pin counts greater than the capacity of a given chassis, the traditional approach has been to use a new and bigger chassis incorporating bigger power supplies, more PC board slots, and a larger Device Under Test (DUT) interface apparatus. To realize pin counts smaller than the maximum available in a given (typically large) chassis, the traditional approach has been to depopulate the chassis by removing PC boards. The pin count of the tester is reduced in this way, but there is still a tremendous expense carried in the product in unused backplanes, power supplies, cabling, and mechanical structure not required for the small number of PC boards in a small pin count configuration.
The exact same arguments hold for the electronic section of the tester. Designing, debugging, and manufacturing different electronic hardware for different sized test systems is very expensive. The electronics in a tester is typically two to five times more expensive than the mechanical portion of a tester and the development costs scale accordingly. Thus, minimizing the number of circuit board types to design, manufacture, and support across a wide range of tester sizes has a huge impact on the tester manufacturer's expenses and inventory costs.
Another problem with conventional test systems having a fixed sized chassis arises from their size and weight. Because ICs are manufactured, packaged and tested in controlled fabrication facilities known as fabs, an important consideration in selecting equipment is the amount of floor space occupied by the equipment. This is often referred to as the equipment footprint. Thus, it is generally desirable that equipment used in the clean room, such as the test system, present as small a footprint as possible. It is also often desirable that equipment be capable of being quickly and easily relocated within the facility from a standby location to a testing area, or between multiple testing areas within the fab or even between multiple fabs, thereby saving on both floor space and investment in testing systems.
Yet another problem with the conventional approach of maintaining different test systems for testing of DUTs having different pin counts is the expense associated with training operators and maintenance technicians on each different test system or differently configured test system. Indeed, because the need for trained operators and maintenance technicians continues for the life of the test system, this expense can be more significant than that of maintaining spare parts for multiple test systems.
Accordingly, there is a need for a test system and method of operating the same that can be quickly and easily scaled to enable testing of a DUT having a number of pins greater than can be accommodated on any single tester, or to simultaneously test a large number of smaller DUTs in parallel on different testers. There is a further need for a test system that conserves floor space in a manufacturing facility by reducing or minimizing system footprint for test systems having larger capacity. There is still a further need for a test system that increases manufacturing efficiency by reducing the volume of spare parts and assembly documentation maintained per test system, and by reducing manufacturing and service training required per test system.
The system and method of the present invention provides these and other advantages over the prior art.